`timescale 1ns / 100ps

// structural model of edge triggered D type

module dtype(Q, nQ, D, Clk, nRst);

output Q, nQ;
input D, Clk, nRst;

wire Q, nQ, D, Clk, nRst, net1, net2, net3, net4;

   nand #1 nand1 ( net1, net3, D, nRst );
   nand #1 nand2 ( net2, net1, net4 );
   nand #1 nand3 ( net3, Clk, net1, net4 );
   nand #1 nand4 ( net4, Clk, net2, nRst );
   nand #1 nand5 ( nQ, nRst, net3, Q );
   nand #1 nand6 ( Q, nQ, net4 );

endmodule