`include "opcodes.v"
`timescale 1ns / 100ps

module control( data, address, control, memory_write, zflag, clock, not_reset );

input [15:0] data;
output [11:0] address;
output [3:0] control;
output memory_write;
input zflag, clock, not_reset;

reg state;
reg [11:0] Program_Counter;
reg [15:0] Instruction_Register;

wire [11:0] operand;
wire [3:0] opcode;
wire branch;

parameter execute_cycle = 0;
parameter fetch_cycle = 1;


   assign operand = Instruction_Register[11:0];
   assign opcode  = Instruction_Register[15:12];

   assign memory_write = (opcode == `STA) & (state == execute_cycle);

   assign address = (state == fetch_cycle) ? Program_Counter : operand;
   assign control = (state == fetch_cycle) ? `NOP : opcode;

   assign branch = (state == execute_cycle) && ((control ==`JMP) ||
                               ((control ==`JMPZ) && (zflag == 1)) ||
                               ((control ==`JMPNZ) && (zflag == 0)));

   always @(posedge clock or negedge not_reset)
      if (!not_reset)
         begin
            Program_Counter <= 0;
            state <= 0;
            Instruction_Register <= 0;
         end
      else
         begin

            if (state == fetch_cycle)
               begin
                  Instruction_Register <= #20 data;
                  state <= #20 execute_cycle;
               end
            else // execute cycle
               begin
                  state <= #20 fetch_cycle;
               end

            if (branch)
               Program_Counter <= #20 operand;
            else if (state == fetch_cycle)
               Program_Counter <= #20 Program_Counter + 1;

         end

endmodule