`timescale 100ps / 10ps // behavioural model of an up/down counter module up_down_count(count, up, down, clock, not_reset); output [3:0] count; input up, down, clock, not_reset; reg [3:0] count; // action on clock rising edge always @(posedge clock) begin if (up & ~down) count = count + 1; if (down & ~up) count = count - 1; if (up & down) count = 0; end // asynchronous "assign" overrides synchronous action always @(not_reset) if (!not_reset) begin assign count = 0; end else begin deassign count; end endmodule