`timescale 100ps / 10ps // structural model of edge triggered D type module dtype(Q, nQ, D, Clk, nRst); output Q, nQ; input D, Clk, nRst; wire Q, nQ, D, Clk, nRst, net1, net2, net3, net4; nand nand1 ( net1, net3, D, nRst ); nand nand2 ( net2, net1, net4 ); nand nand3 ( net3, Clk, net1, net4 ); nand nand4 ( net4, Clk, net2, nRst ); nand nand5 ( nQ, nRst, net3, Q ); nand nand6 ( Q, nQ, net4 ); endmodule