`include "opcodes.v"
`timescale 100ps / 10ps

module alu( zflag, result, inputA, inputB, func);

output [15:0] result;
output zflag;
input [15:0] inputA, inputB;
input [3:0] func;

reg [15:0] result;
wire zflag;

   assign zflag = (inputA == 0);

   always @(inputA or inputB or func)
      case (func)
         `LDA		: result = inputB;
         `ADD		: result = inputA + inputB;
         `SUB		: result = inputA - inputB;
         `AND		: result = inputA & inputB;
         `OR		: result = inputA | inputB;
         `NOT		: result = ~inputA;
         `LSL		: result = inputA << 1;
         `LSR		: result = inputA >> 1;
         default	: result = inputA;
      endcase

endmodule