`timescale 100ps / 10ps

// model file for RS flip flop

module rs_flipflop ( q, not_r, not_s );
  
   input not_r, not_s;
   output q;

   wire q, not_r, not_s;

   // netlist information

   nand gate1 ( q, not_s, not_q );
   nand gate2 ( not_q, not_r, q );

endmodule