`timescale 100ps / 10ps

// stimulus file for RS flip flop

module rs_flipflop_stim1;
  
   reg notR, notS;
   wire Q;

   rs_flipflop rs_instance1 ( Q, notR, notS );

   // stimulus information

   initial
      begin
            notR = 1; notS = 1;
         #1000
            notR = 0;
         #1000
            notR = 1;
         #1000
            notS = 0;
         #1000
            notS = 1;
         #1000
            notR = 0;
         #1000
            notR = 1;
         #1000
            $finish;
      end

   // probe information
   //  - generic verilog commands

   initial
      begin
         $monitor( "Time:",$time,
                   "   notR: %b", notR,
                   "   notS: %b", notS,
                   "   Q: %b",    Q     );
      end

endmodule