`timescale 100ps / 10ps
// stimulus file for RS flip flop

module rs_flipflop_stim2;
  
   reg notR, notS;
   wire Q;

   rs_flipflop rs_instance1 ( Q, notR, notS );

   // stimulus information

   initial
      begin
            notR = 1; notS = 1;
         #1000
            notR = 0;
         #1000
            notR = 1;
         #1000
            notS = 0;
         #1000
            notS = 1;
         #1000
            notR = 0;
         #1000
            notR = 1;
         #1000
	    $display("\n                    Simulation complete\n");
            $stop;
            $finish;
      end

   // probe information
   //  - generic verilog commands

   initial
      begin
         $display("                Time     Inputs    Outputs");
         $display("                       notR  notS     Q");
         $display("                ====   ==========  =======");
         $monitor($time,"     %b    %b       %b", notR, notS, Q);
      end

   // probe information
   //  - Verilog-XL specific commands

   initial
      begin
         $timeformat(-10);
	 $gr_position( "waves", 0,0,600,200);
	 $gr_waves( "not R", notR,
                    "not S", notS,
                    "Q",     Q,
                    "not Q", rs_instance1.not_q);
      end

   // probe information
   //  - ModelSim specific commands

   //VSIM COMMAND: view wave -x 0 -y 300 -width 800 -height 300
   //VSIM COMMAND: add wave -label "not R" notR -label "not S" notS
   //VSIM COMMAND: add wave -label "Q" Q
   //VSIM COMMAND: add wave -label "not Q" rs_instance1/not_q
   //VSIM COMMAND: run -all

endmodule