`include "opcodes.v"
`timescale 100ps / 10ps

module system;

reg Clock, Clear_bar;

processor p1 ( Clock, Clear_bar);

always
  begin
     Clock = 0;
    #250
     Clock = 1;
    #500
     Clock = 0;
    #250
     Clock = 0;
  end

initial
  begin
    Clear_bar = 1;
    #100
    Clear_bar = 0;
    #800
    Clear_bar = 1;
    #100
    Clear_bar = 1;
    #100000
    $display("Too long - giving up");
    $stop;
    $finish;
  end

always @(posedge Clock)
   if ( p1.Control.Program_Counter == 99 )
      begin
         $display("Terminating at instruction 99\n");
         @(posedge Clock);
         @(posedge Clock);
         $stop;
         $finish;
      end

initial
   begin
      $timeformat(-10);
      $gr_position("waves",420,0,700,140);
      $gr_position("regs",0,0,400,600);
      $gr_waves("clock", Clock, "clear_bar", Clear_bar );
      $gr_regs(
               "  Simulation of a Simple Microprocessor",
               "  =====================================",
               "",
               "  State       : %s", State(p1.Control.state),
               "  PC          : %d",p1.Control.Program_Counter,
               "",
               "  Instruction : %d     %s         %d",
                               p1.Control.Instruction_Register,
                               Mnemonic(p1.Control.Instruction_Register),
                               p1.Control.operand,
               "",
               "  Accumulator : %d", p1.Datapath.Accumulator,
               "",
               "  Memory (code)",
               "         [0]  : %d     %s         %d", p1.Memory.Data_stored[0],
                                                Mnemonic(p1.Memory.Data_stored[0]),
                                               Operand(p1.Memory.Data_stored[0]),
               "         [1]  : %d     %s         %d", p1.Memory.Data_stored[1],
                                                Mnemonic(p1.Memory.Data_stored[1]),
                                                Operand(p1.Memory.Data_stored[1]),
               "         [2]  : %d     %s         %d", p1.Memory.Data_stored[2],
                                                Mnemonic(p1.Memory.Data_stored[2]),
                                                Operand(p1.Memory.Data_stored[2]),
               "         [3]  : %d     %s         %d", p1.Memory.Data_stored[3],
                                                Mnemonic(p1.Memory.Data_stored[3]),
                                                Operand(p1.Memory.Data_stored[3]),
               "         [4]  : %d     %s         %d", p1.Memory.Data_stored[4],
                                                Mnemonic(p1.Memory.Data_stored[4]),
                                                Operand(p1.Memory.Data_stored[4]),
               "         [5]  : %d     %s         %d", p1.Memory.Data_stored[5],
                                                Mnemonic(p1.Memory.Data_stored[5]),
                                                Operand(p1.Memory.Data_stored[5]),
               "         [6]  : %d     %s         %d", p1.Memory.Data_stored[6],
                                                Mnemonic(p1.Memory.Data_stored[6]),
                                                Operand(p1.Memory.Data_stored[6]),
               "         [7]  : %d     %s         %d", p1.Memory.Data_stored[7],
                                                Mnemonic(p1.Memory.Data_stored[7]),
                                                Operand(p1.Memory.Data_stored[7]),
               "         [8]  : %d     %s         %d", p1.Memory.Data_stored[8],
                                                Mnemonic(p1.Memory.Data_stored[8]),
                                                Operand(p1.Memory.Data_stored[8]),
               "         [9]  : %d     %s         %d", p1.Memory.Data_stored[9],
                                                Mnemonic(p1.Memory.Data_stored[9]),
                                                Operand(p1.Memory.Data_stored[9]),
               "        [99]  : %d     %s         %d", p1.Memory.Data_stored[99],
                                                Mnemonic(p1.Memory.Data_stored[99]),
                                                Operand(p1.Memory.Data_stored[99]),
               "  Memory (constants)",
               "        [20]  : %d", p1.Memory.Data_stored[20],
               "        [21]  : %d", p1.Memory.Data_stored[21],
               "  Memory (data)",
               "        [22]  : %d", p1.Memory.Data_stored[22],
               "        [23]  : %d", p1.Memory.Data_stored[23],
               "        [24]  : %d", p1.Memory.Data_stored[24],
               "        [25]  : %d", p1.Memory.Data_stored[25],
               "",
               ""
      );
   end


   function [10*8:1] Mnemonic;
      input [15:0] instruction;
      case (instruction[15:12])
         `NOP		: Mnemonic = "NOP";
         `JMP		: Mnemonic = "JMP";
         `JMPZ		: Mnemonic = "JMPZ";
         `JMPNZ		: Mnemonic = "JMPNZ";
         `LDA		: Mnemonic = "LDA";
         `ADD		: Mnemonic = "ADD";
         `SUB		: Mnemonic = "SUB";
         `AND		: Mnemonic = "AND";
         `OR		: Mnemonic = "OR";
         `NOT		: Mnemonic = "NOT";
         `LSL		: Mnemonic = "LSL";
         `LSR		: Mnemonic = "LSR";
         `STA		: Mnemonic = "STA";
         default	: Mnemonic = "*ERR*";
      endcase
   endfunction

   function [11:0] Operand;
      input [15:0] instruction;
      Operand = instruction[11:0];
   endfunction

   function [10*8:1] State;
      input fetch_cycle;
      case (fetch_cycle)
         0	: State = "Execute";
         1	: State = "Fetch";
         default	: State = "*ERR*";
      endcase
   endfunction

//VSIM COMMAND: add wave -label "clock" Clock -label "clear_bar" Clear_bar
//VSIM COMMAND: view list -x 0 -width 450
//VSIM COMMAND: add list -label "***Not much here try verilog_xl.***  state" -unsigned p1/Control/state
//VSIM COMMAND: add list -label "Accumulator" -unsigned p1/Datapath/Accumulator
//VSIM COMMAND: run -all

endmodule