`timescale 100ps / 10ps

// behavioural model of an up/down counter

module up_down_count(count, up, down, clock, not_reset);

output [3:0] count;
input up, down, clock, not_reset;

reg [3:0] count;

   always @(posedge clock or negedge not_reset)

      if (!not_reset)
         // asynchronous reset overrides synchronous action
         begin
            count = 0;
         end
      else
         // action on clock rising edge
         begin
            if (up & ~down) count <= count + 1;
            if (down & ~up) count <= count - 1;
            if (up & down) count <= 0;
         end


endmodule