`timescale 100ps / 10ps

//stimulus file for an up/down counter

module up_down_count_stim;
   reg Up, Down, nReset, Clock;
   wire [3:0] Count;

   up_down_count instance1 ( Count, Up, Down, Clock, nReset );

   always
      begin
              Clock = 0;
         #250 Clock = 1;
         #500 Clock = 0;
         #250 Clock = 0;
      end

   initial
      begin
            nReset = 1;
            Up = 0; Down = 0;
         #1000
            nReset = 0;
         #1000
            nReset = 1;
         #1000
            Up = 1;
         #15000
            Up = 0;
         #1000
            $stop;
            Down = 1;
         #15000
            Down = 0;
         #2000
            $stop;
            Up = 1; Down = 0;
         #4000
            Up = 0; Down = 1;
         #7000
            Up = 1; Down = 0;
         #23000
            $stop;
            $finish;
      end


   // probe information
   //  - Verilog-XL specific commands

   initial
      begin
         $timeformat(-10);
         $gr_position( "waves", 20,20,1000,320);
         $gr_waves( "Clock", Clock,
                 "nReset", nReset,
                 "Up", Up,
                 "Down", Down,
                 "Count_3", Count[3],
                 "Count_2", Count[2],
                 "Count_1", Count[1],
                 "Count_0", Count[0],
                 "Count %d", Count  );
         $gr_position( "regs", 20,380,400,200);
         $gr_regs( "Register Window For UP/DOWN Counter",
                   "===================================",
                   "    Direction of count  %s",
                                     direction(Up,Down),
                   "    Count (binary)      %b", Count,
                   "    Count (decimal)     %d", Count,
                   "    Count (hexadecimal) %h", Count  );
      end


   // probe information
   //  - ModelSim specific commands

   // the following two lines are needed for ModelSim since we
   // can only observe the values of signals (e.g. directStr)
   // not expressions (e.g. direction(Up,Down)) as with
   // Verilog-XL $gr_regs();
   wire [6*8:1] directStr;
   assign directStr = direction(Up,Down);

   //VSIM COMMAND: add wave -label "Clock" Clock  -label "nReset" nReset
   //VSIM COMMAND: add wave -label "Up" Up -label "Down" Down
   //VSIM COMMAND: add wave -label "Count" -unsigned -expand Count
   //VSIM COMMAND: view list -x 0 -width 400
   //VSIM COMMAND: add list -label "Direction of count" -ascii directStr
   //VSIM COMMAND: add list -label "Count (hexadecimal)" -hexadecimal Count
   //VSIM COMMAND: add list -label "Count (decimal)"     -unsigned    Count
   //VSIM COMMAND: add list -label "Count (binary)"      -binary      Count
   //VSIM COMMAND: run -all


   // function declarations

   function [6*8:1] direction;
      input up, down;
      if ({up,down} == 2'b10) direction = "Up";
      else if ({up,down} == 2'b01) direction = "Down";
      else if ({up,down} == 2'b11) direction = "Reset";
      else direction = "Hold";
   endfunction
   
endmodule