`include "opcodes.v"
`timescale 100ps / 10ps

module datapath( data, address, zflag, func, update_z, enable_A, load_A, enable_X, load_X, enable_S, load_S, enable_PC, load_PC, inc_PC, sel_PC, load_MAR, enable_reg, clock, not_reset );

inout [15:0] data;
output [15:0] address;
output zflag;
input [3:0] func;
input update_z;
input enable_A, load_A, enable_X, load_X, enable_S, load_S, enable_PC, load_PC, inc_PC, sel_PC, load_MAR, enable_reg;
input clock, not_reset;

reg [15:0] Acc, X, S, PC, MAR;
reg zflag;

wire [15:0] ALU_output, ALU_input, address;

  assign ALU_input = (enable_A) ? Acc : 16'bz;
  assign ALU_input = (enable_X) ? X : 16'bz;
  assign ALU_input = (enable_S) ? S : 16'bz;
  assign ALU_input = (enable_PC) ? PC : 16'bz;

  assign address = (sel_PC) ? PC : MAR;
  alu ALU ( alu_zflag, ALU_output, ALU_input, data, func);

  always @(posedge clock)
    begin
      if (update_z) zflag = alu_zflag;
      if (load_A) Acc = ALU_output;
      if (load_X) X = ALU_output;
      if (load_S) S = ALU_output;
      if (load_PC) PC = ALU_output;
      else if (inc_PC) PC = PC + 1;
      if (load_MAR) MAR = ALU_output;
    end

   assign data = ( enable_reg ) ? ALU_input : 16'bz;

   always @(not_reset)
      if (!not_reset)
         begin
            assign PC = 0;
         end
      else
         begin
            deassign PC;
         end

endmodule