`timescale 100ps / 10ps

module processor( Clock, notReset );

input Clock, notReset;

wire [15:0] Data_bus;
wire [15:0] Address;
wire [3:0] Function;
wire Zflag, Mem_Write;

   control Control ( Data_bus, Function, Update_Z, Enable_ACC, Load_ACC, Enable_X, Load_X, Enable_S, Load_S, Enable_PC, Load_PC, Inc_PC, Sel_PC, Load_MAR, Enable_reg, Mem_Write, Zflag, Clock, notReset );
   datapath Datapath ( Data_bus, Address, Zflag, Function, Update_Z, Enable_ACC, Load_ACC, Enable_X, Load_X, Enable_S, Load_S, Enable_PC, Load_PC, Inc_PC, Sel_PC, Load_MAR, Enable_reg, Clock, notReset );
   memory Memory ( Data_bus, Address, Mem_Write, Clock );

endmodule