`include "opcodes.v" `timescale 100ps / 10ps module system; reg Clock, Clear_bar; processor p1 ( Clock, Clear_bar); always begin Clock = 0; #250 Clock = 1; #500 Clock = 0; #250 Clock = 0; end initial begin Clear_bar = 1; #100 Clear_bar = 0; #800 Clear_bar = 1; #100 Clear_bar = 1; #500000 $display("Too long - giving up"); $stop; $finish; end always @(posedge Clock) if ( p1.Datapath.PC == 99 ) begin $display("Terminating at instruction 99\n"); @(posedge Clock); @(posedge Clock); $stop; $finish; end initial begin $timeformat(-10); $gr_position("waves",650,150,490,140); $gr_position("regs",0,0,640,850); $gr_waves("clock", Clock, "clear_bar", Clear_bar ); $gr_regs( ".................... ..........................................................", ":Control : : Datapath:", ": : : +-----------------------%d ---+ :", p1.Datapath.ALU_input, ": State:[%b] : : | | :", p1.Control.state, ": %s : : | | | :", Fetch(p1.Control.fetch), ": %s : : |%s [ACC %d ]%s | | :", OpFetch(p1.Control.op_fetch),Arrow(p1.Control.enable_Acc), p1.Datapath.Acc, Arrow(p1.Control.load_Acc), ": %s : : | | | :", Execute(p1.Control.execute), ": : : |%s [ X %d ]%s | | :",Arrow(p1.Control.enable_X), p1.Datapath.X, Arrow(p1.Control.load_X), ":Opcode Add. Mode : : | | | +%d + :",p1.Datapath.data, ": %s %s : : |%s [ S %d ]%s | | | | :",Mnemonic(p1.Control.Instruction_Register),AddMode(p1.Control.Instruction_Register),Arrow(p1.Control.enable_S), p1.Datapath.S, Arrow(p1.Control.load_S), ": : : +%s | | v v | :",Arrow(p1.Control.enable_reg), ":IR:[%d ] : : | |%s [ PC %d ]%s | +---+ +---+ | :",p1.Control.Instruction_Register,Arrow(p1.Control.enable_PC), p1.Datapath.PC, Arrow(p1.Control.load_PC), ": ^ : : | | | | \\ \\ / / | :", ": | : : | %s +--%s --+ | \\ V / | :", Star(2),INC(p1.Control.inc_PC), ": | : : | %s<---+ | Z=%d\\%s / | :", Star(p1.Control.sel_PC), p1.Zflag, ALUFunc(p1.Datapath.func), ": | : : | +----%s | +---+ | :", Star(0), ": | : : | | %s<---[MAR %d ]%s | | | :", Star(!p1.Control.sel_PC), p1.Datapath.MAR, Arrow(p1.Control.load_MAR), ": | : : | | %s | | | :", Star(3), ": | : : | | +---%d ---+ | :", p1.Datapath.ALU_output, ":......|...........: ..|..|.................................................|..", " | | | | ", " | | | | ", " | v | Data_bus(%d ) | ", p1.Data_bus, " %s ", Big_bus(p1.Mem_Write), " | ^ ", " | | ", " | v ", " | +----------------------------------+", " | %s | |", WnR(p1.Mem_Write), " | ------->| |", " | | mem(%d ):[%d ] |", p1.Address[11:0], p1.Memory.Data_stored[p1.Address], " | Address(%d ) | |", p1.Address, " +--------------->| |", "Simulation of a | Memory|", "Simple CISC Style Processor +----------------------------------+", "", "................................................................................", "CODE: DATA:", " m( 0):[%d ](%s %s ) m(150):[%d ] m(151):[%d ] m(152):[%d ]", p1.Memory.Data_stored[0], Mnemonic(p1.Memory.Data_stored[0]), AddMode(p1.Memory.Data_stored[0]), p1.Memory.Data_stored[150], p1.Memory.Data_stored[151], p1.Memory.Data_stored[152], " m( 1):[%d ](%s %s ) m(153):[%d ]", p1.Memory.Data_stored[1], Mnemonic(p1.Memory.Data_stored[1]), AddMode(p1.Memory.Data_stored[1]), p1.Memory.Data_stored[153], " m( 2):[%d ](%s %s ) m(200):[%d ] m(201):[%d ] m(202):[%d ]", p1.Memory.Data_stored[2], Mnemonic(p1.Memory.Data_stored[2]), AddMode(p1.Memory.Data_stored[2]), p1.Memory.Data_stored[200], p1.Memory.Data_stored[201], p1.Memory.Data_stored[202], " m( 3):[%d ](%s %s ) m(203):[%d ] m(204):[%d ]", p1.Memory.Data_stored[3], Mnemonic(p1.Memory.Data_stored[3]), AddMode(p1.Memory.Data_stored[3]), p1.Memory.Data_stored[203], p1.Memory.Data_stored[204], " m( 4):[%d ](%s %s ) m(210):[%d ] m(211):[%d ] m(212):[%d ]", p1.Memory.Data_stored[4], Mnemonic(p1.Memory.Data_stored[4]), AddMode(p1.Memory.Data_stored[4]), p1.Memory.Data_stored[210], p1.Memory.Data_stored[211], p1.Memory.Data_stored[212], " m( 5):[%d ](%s %s ) m(213):[%d ] m(214):[%d ]", p1.Memory.Data_stored[5], Mnemonic(p1.Memory.Data_stored[5]), AddMode(p1.Memory.Data_stored[5]), p1.Memory.Data_stored[213], p1.Memory.Data_stored[214], " m( 6):[%d ](%s %s ) m(220):[%d ] m(221):[%d ] m(222):[%d ]", p1.Memory.Data_stored[6], Mnemonic(p1.Memory.Data_stored[6]), AddMode(p1.Memory.Data_stored[6]), p1.Memory.Data_stored[220], p1.Memory.Data_stored[221], p1.Memory.Data_stored[222], " m( 7):[%d ](%s %s ) m(223):[%d ] m(224):[%d ]", p1.Memory.Data_stored[7], Mnemonic(p1.Memory.Data_stored[7]), AddMode(p1.Memory.Data_stored[7]), p1.Memory.Data_stored[223], p1.Memory.Data_stored[224], "" ); end function [4*8:1] OpMnemonic; input [11:0] opcode; case (opcode) `NOP : OpMnemonic = "NOP"; `BA : OpMnemonic = "BA"; `BEQ : OpMnemonic = "BEQ"; `BNE : OpMnemonic = "BNE"; `LDX : OpMnemonic = "LDX"; `LDS : OpMnemonic = "LDS"; `LDA : OpMnemonic = "LDA"; `ADD : OpMnemonic = "ADD"; `SUB : OpMnemonic = "SUB"; `AND : OpMnemonic = "AND"; `OR : OpMnemonic = "OR"; `COM : OpMnemonic = "COM"; `LSL : OpMnemonic = "LSL"; `LSR : OpMnemonic = "LSR"; `STA : OpMnemonic = "STA"; `STX : OpMnemonic = "STX"; `STS : OpMnemonic = "STS"; default : OpMnemonic = "****"; endcase endfunction function [5*8:1] ALUFunc; input [3:0] opcode; case (opcode) `justA : ALUFunc = " R"; `justB : ALUFunc = " M"; `AaddB : ALUFunc = " R+M"; `AsubB : ALUFunc = " R-M"; `AandB : ALUFunc = " R&M"; `AorB : ALUFunc = " R|M"; `notA : ALUFunc = " ~R"; `lslA : ALUFunc = " R<<1"; `lsrA : ALUFunc = " R>>1"; default : ALUFunc = "*ERR*"; endcase endfunction function [11*8:1] AddMode; input [15:0] instruction; case (instruction[3:0]) `DIRECT : AddMode = "DIRECT"; `INHERENT : AddMode = "INHERENT"; `IMMEDIATE : AddMode = "IMMEDIATE"; `INDEXED : AddMode = "INDEXED"; `PC_RELATIVE : AddMode = "PC_RELATIVE"; default : AddMode = "***********"; endcase endfunction function [4*8:1] Mnemonic; input [15:0] instruction; Mnemonic = OpMnemonic(instruction[15:4]); endfunction function [2*8:1] Star; input [1:0]sig; case (sig) 0 : Star = "||"; 1 : Star = "|*"; 2 : Star = "/|"; 3 : Star = "\\|"; default : Star = "||"; endcase endfunction function [6*8:1] Arrow; input sig; Arrow = (sig) ? "<-<-<-" : "<-----"; endfunction function [7*8:1] Fetch; input fetch; Fetch = (fetch) ? "Fetch" : ""; endfunction function [7*8:1] OpFetch; input op_fetch; OpFetch = (op_fetch) ? "OpFetch" : ""; endfunction function [7*8:1] Execute; input execute; Execute = (execute) ? "Execute" : ""; endfunction function [4*8:1] INC; input inc; case (inc) 0 : INC = "[+0]"; 1 : INC = "[+1]"; default : INC = "****"; endcase endfunction function [5*8:1] WnR; input signal; case (signal) 0 : WnR = "read"; 1 : WnR = "write"; default : WnR = "*ERR*"; endcase endfunction function [5*8:1] Cond; input [11:0] opcode; input signal; case (opcode) `BA : Cond = (signal) ? "TRUE" : "FALSE"; `BEQ : Cond = (signal) ? "TRUE" : "FALSE"; `BNE : Cond = (signal) ? "TRUE" : "FALSE"; default : Cond= ""; endcase endfunction function [75*8:1] Big_bus; input [3:0] signal; case (signal) 0 : Big_bus = "==+================+============================*=======================+=="; 1 : Big_bus = "==+================*============================+=======================+=="; default: Big_bus = "==+================+============================+=======================+=="; endcase endfunction endmodule